How SEQ executes instructions
The original SEQ executes only one instruction per clock cycle.
If you execute one instruction on hardware (a),
the combinational logic takes 300ps (s/trillion), and
writing the value to the register on the clock takes 20ps, so it takes 320ps in total.
If you run I1, I2, I3 on hardware (a),
it executes 3 instructions, I1 I2 I3, so it takes 320 * 3 = 960ps.
Measuring SEQ performance
There are two concepts for measuring performance.
Latency of SEQ
Latency is expressed as the time it takes to execute one instruction.
So the latency of the SEQ above is 320ps.
Throughput of SEQ
Throughput is expressed as the number of instructions executed per second.
The SEQ above executes 1 instruction every 320ps, so it processes 3.12 billion instructions per 1s.
That's too long, so if we express throughput with GIPS, the convention of counting in bundles of a billion instructions, it's 3.12 GIPS.
So the throughput of the SEQ above is 3.12 GIPS.
Why pipelining?
If we could execute several instructions at the same time without changing SEQ's order of work, we could get a faster speed.
One instruction can be split into several stages (Fetch, Decode, Execute, Memory, Writeback, PC update),
and by splitting an instruction into a suitable number of pieces, we can execute several instructions at the same time without changing the order they complete in.
Let's say the hardware is set up like the above.
It computes in A, the clock rises and it's written to the first register,
computes in B, the clock rises and it's written to the second register,
computes in C, the clock rises and it's written to the third register,
and repeats this.
Let's say each section runs like the above with the pipeline.
For example, after A finishes Fetch, B does Fetch during the Decode stage, and that's how several instructions get executed at the same time.
If we number each section and look at the hardware state, it looks like this.
Measuring pipelining performance
The way we measure it is exactly the same as SEQ's throughput and latency.
There's just a bit to think about in how we get the throughput.
Latency of Pipelining
For one instruction to finish executing, it has to go through stages A, B, and C.
One stage completes per clock cycle, so multiplying the clock cycle of 120ps by 3 gives 360ps.
So the latency of the pipelining above is 360ps.
Throughput of Pipelining
The above only executes 3 instructions, but throughput is calculated assuming instructions run repeatedly for 1 second,
so let's assume we have to keep executing the instructions I1 I2 I3 I1 I2 I3 I1....
We need to find the number of instructions executed in 1 second,
and since a huge number of instructions run in 1 second, even if we ignore the two side parts the value won't be very different from the number of instructions actually executed.
So if we remove the side parts for the throughput calculation and only look at the part from 0ps to 600ps, the instructions run in the form shown above.
Now, for the throughput calculation, let's think about the following.
Hardware split into N parts will run N stages at the same time. (In the example, N = 3)
Also, to execute one instruction it has to go through stages A, B, and C, and during a single cycle stages A, B, and C are all running.
So if we think of it as one instruction being executed because stages A, B, and C all run during one clock cycle,
the number you get by dividing 1 second into cycle units (above, 1s / 120ps) is the same as the number of instructions executed in 1 second.
In reality, during one cycle one stage of I1, one stage of I2, and one stage of I3 run,
but the point is that in the end it's almost the same as the number of instructions executed in 1 second.
Calculating based on the facts above,
if we think of one instruction as running for 120ps,
we get the ratio 1 Instruction : 120ps = 8333333333.33 Instruction : 1s.
It executes about 8.3333 billion per second, so expressed in GIPS, which bundles them by the billion, it's about 8.33333 GIPS.
So the throughput of the pipelining above is about 8.33 GIPS.
SEQ vs Pipelining performance comparison
Latency : Pipelining's latency is about 1.12 (360 / 320) times longer than SEQ's latency.
Throughput : Pipelining's throughput is about 2.67 (8.33 / 3.12) times longer than SEQ's latency.
Pipelining increased instruction processing time a little, by 1.12 times, compared to SEQ, but gained 2.67 times the throughput,
so we can sum it up as getting better performance.